In contemporary data processing systems, it is conventional for a (CPU) to exert exclusive control over a memory subsystem which is concurrently accessible to the CPU and other system elements (peripheral devices, other processing subsystems, etc.). For instance, present day 80386 and 80486 processing units made by Intel Corporation (Santa Clara, Calif.) have a lock signal output pin useful for that purpose.
Generally, the lock signal is used by the CPU to secure continuous ("atomic") memory access while the CPU is performing a Read Modify Write operation, relative to data in the memory subsystem, so that integrity of such data can not be compromised as a result of actions performed concurrently by the CPU and other system elements. In such cases, a semaphore signal (memory operand) is used to control access to some resource such as memory, a program or a device. Before the CPU or other system element can gain control of the associated resource, it must first attempt to read the semaphore, ascertain that it is marked available, and then mark it "in use" (i.e. modify the semaphore and write the modified semaphore to memory). If the semaphore is marked "in use" when read, the CPU or other element can not access the respective resource.
In order for this process to work correctly, the semaphore can only be susceptible of modification by one system entity at any time (e.g. the CPU or another system element). Otherwise, the state of the semaphore could be misread or miswritten, resulting in two entities (or none) getting access to the associated resource, with unpredictable and usually erroneous results.
It is also conventional in such systems to have the memory subsystem control access to a system bus which links it with the other system elements mentioned above, and to carry out that function transparent to the CPU when the CPU lock signal is inactive. This type of arrangement can improve CPU performance, but it also prevents the CPU from being able to detect external contention for memory access when such detection would be useful.
For instance, certain CPU configurations (particularly, CPUs with internal cache), may be capable of extending their lock control over memory access continuously while carrying out multiple atomic access operations consecutively. This could cause erroneous operation of the external elements or the memory subsystem if external access is blocked for too long a time (e.g. it could block timely refresh of memory cells requiring such) or cause overrun conditions relative to external devices or elements).
This potential problem has recognized earlier, and avoided by means of a prior art "back off" (BOff) circuit mechanism. That circuit presents a backoff signal to the CPU when external contention for memory access coincides with a CPU "Locked Write" operation relative to memory (i.e. the Write portion of an atomic Read Modify Write operation). The backoff signal forces the CPU unconditionally to release its lock signal within a predetermined time (one CPU clock period) after activation of the backoff signal, and the backoff signal is tit led to bring about this release at the end of the current locked write operation. Thus, the current atomic operation is completed if its end coincides with the end of the current locked write.
A problem presently recognized, however, is that an atomic operation which would require a single read and a single write to process aligned (semaphore) data (e.g. data words located on word boundaries of a memory system accessed a word at a time), would require more read and write operations to process unaligned data (e.g. data words distributed over two word storage positions in the same memory system); i.e. two read operations to read a word from two word storage locations, and two write operations to write a modified word to the same two locations.
Thus, if the backoff signal is activated during other than the last write of an atomic operation relative to unaligned data, the lock signal would be released before the end of that operation, and the (semaphore) data written would be incomplete or erroneous. If that occurred, the integrity of the associated data or resource could be compromised (e.g. by external access to the affected semaphore data before the CPU has a chance to complete the operation).
Although the statistical probability of this chain of circumstances occurring--the CPU being caused to prematurely end an atomic operation relative to an unaligned operand which is then externally accessed before the CPU can complete its operation (i.e. within a short interval on the order of tens of microseconds)--is very small, the possibility that it could occur is considered sufficiently troublesome to require that it be avoided completely. The present invention accomplishes that purpose. It also provides certain operational advantages over the BOff (prior art) lock release circuit mechanism that tend to improve overall CPU performance without significantly degradating external access to memory.